1. Field of the Invention
The present invention relates to superconducting logic circuits and more particularly to superconducting logic circuits formed from asynchronous SFQ logic gates suitable for use in combinational logic circuits.
2. Description of the Prior Art
Superconducting logic circuits utilizing so-called Josephson junctions are known in the art. Examples of such circuits are disclosed in U.S. Pat. Nos. 4,092,553; 4,097,765; 4,371,796; 4,501,975; 4,672,244; 5,051,627 and 5,233,244. Such superconducting logic circuits are also disclosed in xe2x80x9cRSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Terahertz-Clock-Frequency Digital Systemsxe2x80x9d by Likharev et al., IEEE Transactions on Applied Superconductivity, Vol. 1, No. 1, pp 3-28, March 1991.
Such superconducting logic circuits are known to include one or more Josephson junctions. At cryogenic temperatures, such Josephson junctions exhibit non-linear characteristics which are suitable for logic circuits. More particularly, when cooled, such Josephson junctions exhibit zero resistance when subjected to biasing currents less than the critical current Ic. When an electrical current greater than the critical current is applied to the input of a Josephson device, the Josephson junction switches to a finite impedance state. Normally, such Josephson junctions are biased to a current value Ib, just less than the critical current value Ic. As such, relatively small signal currents can be used to change the state of the junction. Unfortunately, such Josephson junctions are known to exhibit latching characteristics. More specifically, due to the hysteretic chracteristic of a Josephson junction, simply removing the input current does not change the state of the device. In order to unlatch the device, it is also necessary to remove the biasing current. As discussed in xe2x80x9cRFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Terahertz-Clock Frequency Digital Systems,xe2x80x9d supra, such latching characteristics limit the bandwidth of such logic circuits.
In order to overcome this problem, digital logic circuits have been developed which rely on the response of Josephson junctions to a short voltage pulse, rather than the resistive characteristics. When such Josephson junctions are biased by a biasing current Ib, less than the critical current Ic, a short voltage pulse V(t) induces a change in the phase of magnetic flux which generates a so-called single flux quantum (SFQ) pulse at the junction. Rather than using the change in resistive state for coding binary information, the newer circuits utilize the change in flux phase for coding binary information. Logic circuits based on SFQ pulses offer a drastically improved operating speed for logic circuits and have become known as rapid single flux quantum (RSFQ) logic circuits. As discussed in the Likharev et al. article, such RSFQ logic circuits can operate at speeds above 300 GHz; a drastic improvement over the logic circuits based on resistive state changes of superconducting devices having operating speeds of only a few gigahertz.
In general, such RSFQ logic circuits are synchronous in nature and depend on the timing of the arrival of the pulses at the inputs. As such, RSFQ logic circuits require clock inputs at the gate level. Such clock signals need to be pipelined to each gate in the circuit. Although gate level pipelining is acceptable in some applications, the need for gate level pipelining in other applications results in a relatively high overhead for clock distribution and can raise issues with respect to the latency. As such, asynchronous superconducting logic circuits have been developed. An example of such an asynchronous superconducting logic circuit is disclosed in U.S. Pat. No. 5,598,105. The asynchronous SFQ logic circuit disclosed in the ""105 patent is formed from logic cells in which each logic cell includes an AND gate and an OR gate. The cell includes a pair of inputs connected to both the AND and the OR gate. Although such logic circuits are tolerant of differences in the arrival times of the voltage pulses at the inputs, the topology of the elementary logic cell requires significant real estate and increased power overhead. Thus, there is a need for an asynchronous superconducting logic circuit which can be made denser with reduced power overhead and at the same time eliminate the need to pipeline clock signals to all gates.
Briefly, the present invention relates to an asynchronous SFQ logic cell that is amenable to being used in combination logic circuits. Rather than encode each digital logic bit as one SFQ pulse, each logic bit is encoded as a series of SFQ pulses. As such, merge and join circuits can be used for elementary logic cells to form asynchronous combinational logic circuits in accordance with the present invention. Such circuits are relatively faster and denser as well as more compatible with existing synchronous SFQ logic circuits.